The card provides an easy to use parallel interface between the processors using First-In First-Out (FIFO) hardware and a simple message passing software protocol. Voltage level shifting components are included so that both 3V3 and 5V co-processors can be connected directly. Most likely the co-processor will be a RaspberryPi, but the interface is suitable for other processors and systems, including Arduinos, Teensy and PIC MCUs.
FIFO based operation ensures all key timing requirements are handled by the board, so that any co-processor can be easily interfaced without needing to run bare-metal, timing critical code. e.g. A Raspberry Pi running a full Rasbian (Linux) distribution and a relatively low performance language like Python is perfectly suitable. This kind of co-processor could make some of its own OS resources available to the CPC, for example an SD card interface, timers, serial links etc.
The board has a convenient connector to allow a RaspberryPi Zero to be plugged directly into the back of the card and powered from the FIFO card itself. Other Pis will fit (although access to the HDMI port is awkward at the bottom of the card), but most likely will need a small 'riser' or 'spacer' inserted in the GPIO connector. Many other CPUs including Arduino, Teensy, ChipKit, PIC MPUs can be connected with a suitable cable adapter.
Full software interface and hardware construction details are provided on the project's GitHub web pages.
All programs and data files in this project are made available under the terms of the GNU General Public License v3.