\n
![\"Recommended](\"\/wp-content\/uploads\/2017\/06\/Recommended-trace-widths-and-spacing.jpg\")
\n[66] For outer layers, the distance between the trace and copper pads should satisfy the requirements shown in
\nfigure 43.<\/p>\n
[65] The width and spacing of copper traces vary according to the thickness of the copper material and which
\nlayer the trace is located. Recommended trace widths and spacing for inner and outer layers of various copper
\nthicknesses is shown in table 8.<\/p>\n
Table 8: Recommended trace widths and spacing.
\n
\n[66] For outer layers, the distance between the trace and copper pads should satisfy the requirements shown in
\nfigure 43.<\/p>\n
![\"solder](\"\/wp-content\/uploads\/2017\/06\/solder-mask-opening.jpg\")
<\/p>\n
Figure 43: Recommended spacing between trace and pads.<\/p>\n
[67] The distance between outer layer traces, inner layer power\/ground planes and ground bus traces to the
\nboard edge should be greater than 20mil.<\/p>\n
[68] There should not be any traces going through the metal shell of components (e.g. heatsink). The region of
\ncomponents\u2019 metal shell should have a 1.5mm clearance area around it.<\/p>\n
![\"components\u2019](\"\/wp-content\/uploads\/2017\/06\/components\u2019-metal-shell.jpg\")
<\/p>\n
Figure 44: Clearance area of components with metal cases.<\/p>\n
[69] Distance from the trace to non-plated through holes is summarised in table 9.
\nTable 9: Distance from the trace to the edge of NPTHs.<\/p>\n
![\"Distance](\"\/wp-content\/uploads\/2017\/06\/Distance-from-the-trace-to-the-edge-of-NPTHs.jpg\")
<\/p>\n
[70] \u00a0Asymmetry should be avoided in the trace and connected solder pads.<\/p>\n
![\"trace\"](\"\/wp-content\/uploads\/2017\/06\/trace.jpg\")
<\/p>\n
Figure 45: Symmetric and asymmetric traces<\/p>\n
[71] Traces should start from the center of solder pads<\/p>\n
![\"symmetric](\"\/wp-content\/uploads\/2017\/06\/symmetric-trace.jpg\")
<\/p>\n
Figure 46: Starting position of the trace to the pad.<\/p>\n
Figure 46: Starting position of the trace to the pad.<\/p>\n
![\"Starting](\"\/wp-content\/uploads\/2017\/06\/Starting-position-of-the-trace-to-the-pad.jpg\")
<\/p>\n
[72] When the width of the trace is wider than the pad, the trace should not overlap the pad. The trace width
\nshould be reduced at the point of contact as shown in figure 48. When adjacent pins of fine pitch components
\nneed to be connected, the trace should not run directly between the pads. Instead, it should run outside of the
\nrow and connect as shown in figure 49.<\/p>\n
![\"trace](\"\/wp-content\/uploads\/2017\/06\/trace-width-reduced1.jpg\")
<\/p>\n
Figure 48: Connecting the trace and pad when the trace width is larger.<\/p>\n
![\"Connecting](\"\/wp-content\/uploads\/2017\/06\/Connecting-the-trace-and-pad.jpg\")
<\/p>\n
Figure 49: Connecting adjacent pads of fine pitch components<\/p>\n
[73] The below designs are recommended for ensuring a strong connection between a trace and hole.<\/p>\n
![\"connection](\"\/wp-content\/uploads\/2017\/06\/connection-between-a-trace-and-hole.jpg\")
<\/p>\n
Figure 50: Connections between the trace and holes<\/p>\n
[74] When the traces on the same layer are unevenly distributed, or the copper distribution in different layers is
\nasymmetric, including a hatched style copper pour grid into the design is recommended<\/p>\n
[75] If there is a large section of the board without copper, copper pour can be used to even out the copper
\ndistribution.<\/p>\n
[76] Recommended copper grid size is about 25mil x 25mil.<\/p>\n
![\"copper](\"\/wp-content\/uploads\/2017\/06\/copper-grid-size.jpg\")
<\/p>\n
Figure 51: Copper grid design.<\/p>\n
More Chapters:<\/strong> 7.1 Trace Width, Spacing and Routing Requirements [65] The width and spacing of copper traces<\/p>\n","protected":false},"author":40,"featured_media":15721,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_lmt_disableupdate":"","_lmt_disable":"","_price":"","_stock":"","_tribe_ticket_header":"","_tribe_default_ticket_provider":"","_tribe_ticket_capacity":"0","_ticket_start_date":"","_ticket_end_date":"","_tribe_ticket_show_description":"","_tribe_ticket_show_not_going":false,"_tribe_ticket_use_global_stock":"","_tribe_ticket_global_stock_level":"","_global_stock_mode":"","_global_stock_cap":"","_tribe_rsvp_for_event":"","_tribe_ticket_going_count":"","_tribe_ticket_not_going_count":"","_tribe_tickets_list":"[]","_tribe_ticket_has_attendee_info_fields":false,"iawp_total_views":0,"footnotes":""},"categories":[1],"tags":[649,4,648],"class_list":["post-15705","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news","tag-dfm-pcb","tag-pcb","tag-pcb-dfm"],"yoast_head":"\n
\n1.\u00a0Brief Introduction<\/a>
\n2.\u00a0Seeed Fusion PCB Specification<\/a>
\n3.\u00a0Panelization and Bridge Design<\/a>
\n4.\u00a0Component Layout Considerations<\/a>
\n5.\u00a0PCB Hole design<\/a>
\n6.\u00a0Solder Mask Design<\/a>
\n8.\u00a0Silkscreen Design<\/a>
\n9.\u00a0PCB Lamination Structure<\/a>
\n10.\u00a0PCB Dimensions Specification<\/a>
\n11.\u00a0Fiducial Mark Design<\/a>
\n12.\u00a0Surface Treatment<\/a>
\n13.\u00a0Files for Manufacture Requirements<\/a>
\n14.\u00a0Appendix\u00a0<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"