{"id":33157,"date":"2020-06-01T18:18:22","date_gmt":"2020-06-01T10:18:22","guid":{"rendered":"\/blog\/?p=33157"},"modified":"2022-05-30T17:48:21","modified_gmt":"2022-05-30T09:48:21","slug":"10-things-you-should-know-about-risc-v-in-2020-m","status":"publish","type":"post","link":"https:\/\/www.seeedstudio.com\/blog\/2020\/06\/01\/10-things-you-should-know-about-risc-v-in-2020-m\/","title":{"rendered":"What is RISC-V\uff1f10 Things You Should Know About RISC-V in 2020"},"content":{"rendered":"\n
\"Is<\/figure><\/div>\n\n\n\n

What is RISC-V<\/h2>\n\n\n\n

RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. <\/p>\n\n\n\n

Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. <\/p>\n\n\n\n

A number of companies are offering or have announced RISC-V hardware, open-source operating systems are available and the instruction set is supported in several popular software toolchains.<\/p>\n\n\n\n

Two Kinds of ISA(CISC vs RISC)<\/h2>\n\n\n\n
\"RISC<\/figure><\/div>\n\n\n\n

CISC – Complex Instruction Set Computer<\/strong><\/p>\n\n\n\n

The CISC contains not only the common instructions of the processor but also a lot of uncommon instructions (the 28th principle, 80% of the instructions used in the program operation, only 20% of all instructions. <\/p>\n\n\n\n

There are many instructions, the typical representative is Intel’s x86 architecture. x86-64 is a 64-bit extension of the x86 architecture, designed by AMD and also known as AMD64.<\/p>\n\n\n\n

RISC – Reduced Instruction Set Computer<\/strong><\/p>\n\n\n\n

Reduced instruction set architecture contains only the instructions commonly used by the processor. For less commonly used operations, the same effect can be achieved by executing multiple commonly used instructions. The reduced instruction set represents more MIPS, RISC-V, Power, Alpha, etc.<\/p>\n\n\n\n

Why does Instruction Set Architecture Matter?<\/h2>\n\n\n\n

The ISA somehow decides the application. It is common sense that the world’s most famous 2 ISA are X86 architecture and ARM architecture. Their application fields are totally different.<\/p>\n\n\n\n

99%+ of laptops, desktops, and servers are based on X86 or AMD64 ISA. The IPs belong to Intel and AMD.<\/p>\n\n\n\n

99+ mobile phones and tablets are based on ARM ISA, and the IPs are divided into A series, R series, and M series.<\/p>\n\n\n\n

While RISC-V is very suitable for use in some specific application fields such as storage, edge computing, and AI applications. <\/p>\n\n\n\n

The different applications field makes it possible for RISC-V to compete with ARM and X86.<\/p>\n\n\n\n

What’s Different About RISC-V?<\/h2>\n\n\n\n

Compared to ARM and X86, RISC-V has below advantages:<\/p>\n\n\n\n

Free<\/strong>: RISC-V is open-source, there is no need to pay for the IP.<\/p>\n\n\n\n

Simple<\/strong>: RISC-V is far smaller than other commercial ISAs.<\/p>\n\n\n\n

Modular<\/strong>: RISC-V has a small standard base ISA, with multiple standard extensions.<\/p>\n\n\n\n

Stable<\/strong>: Base and first standard extensions are already frozen. There is no need to worry about major updates.<\/p>\n\n\n\n

Extensibility<\/strong>: Specific functions can be added based on extensions. There are many more extensions are under development, such as Vector.<\/p>\n\n\n\n

<\/p>\n\n\n\n

ISA Base and Extensions of RISC-V<\/h2>\n\n\n\n

As mentioned earlier, the RISC-V instruction set has modular characteristics. The instruction set is organized in a modular manner. Each module is represented by an English letter. <\/p>\n\n\n\n

The instruction set includes the standard part and the extension part. The standard part must be implemented. <\/p>\n\n\n\n

For example<\/strong>:<\/p>\n\n\n\n

If you want to implement a 32-bit architecture RISC-V processor, the RV32I instruction set must be implemented on the hardware (machine mode must also be implemented in privileged mode).<\/p>\n\n\n\n

The basic integer ISA and the machine privilege ISA provide the functions required by the basic general-purpose CPU. Developers can also enhance the processor’s functionality by adding extensions to ISA. There are already many standard extensions, such as the approved MAFDGQ.<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

What’s the downside of RISC-V?<\/h2>\n\n\n\n

While there are many advantages of RISC-V, as a new player, there are some downsides that users will need to take into consideration when using it.<\/p>\n\n\n\n

The compatibility of different RISC-V ISAs<\/strong>. Since RISC-V is open source, there will be more and more IPs based on RISC-V, the RISC-V Foundation will need to make sure there is only one standard.<\/p>\n\n\n\n

The ecosystem is not mature enough<\/strong>. It needs a lot of around the ISA to design a real chip, while the RISC-V will have to re-create or at least adopt all the chip design ecosystems that a dominant ISA already has for a very long time. <\/p>\n\n\n\n

It still takes time for implementation.<\/strong> Even though there are a lot of RISC-V SoCs working fine under some applications, it is still a long way to verify and optimize the implementation in real-life applications.<\/p>\n\n\n\n

Linux on RISC-V, what’s the latest stage?<\/h2>\n\n\n\n

Back in 2018, SiFive, one of the most active members of the RISV-V Foundation, has already released a board called HiFive that was capable of running Linux on it. <\/p>\n\n\n\n

\"Is<\/figure><\/div>\n\n\n\n

Despite the price being up to $999, it is still quite an exciting board for the community.<\/p>\n\n\n\n

In 2020, with the development of Linux on RISC-V, we have seen an implementation of Linux NOMMU version on the Kendrtyte K210, a RISC-V SoC that is under $10. <\/p>\n\n\n\n

Although there is only 8MB RAM and no MMU, this has still become a big encouragement for the community.<\/p>\n\n\n\n

As a member of the Open Source community, Seeed has a series of products based on the Kendryte K210 sold on the online store, such as the MAix Bit<\/a>, the Maixduino Kit<\/a>, and the Grove AI HAT for Raspberry Pi<\/a>.<\/p>\n\n\n\n

How Many RISC-V SoCs have been implemented?<\/h2>\n\n\n\n

From the information of RISC-V GitHub, there are at least more than 13 commercial implementations for RISC-V, and 9 SoCs have been released, which include solutions from companies like Gigadevice, GreenWave, and SiFive.<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

For those companies mentioned above, Seeed has also provided development boards. Such as the Wio Lite RISC-V<\/a>, incorporating the GD32 from Gigadevice.<\/p>\n\n\n\n

The RISC-V International Association Has Been Incorporated in Switzerland <\/h2>\n\n\n\n

Although the RISC-V project was initially created in the US, although there have not been any export restrictions on RISC-V in the US and they have complied with all US laws, the association still decided to move out of the US, in order to alleviate uncertainty going forward.<\/p>\n\n\n\n

So in March 2020, the RISC-V international association has been officially incorporated in Switzerland. And there are already 500+ members.<\/p>\n\n\n\n

\"RISC-V<\/figure><\/div>\n\n\n\n

It is RISC-V 10 Years Birthday<\/h2>\n\n\n\n

It is hard to believe that the RISC-V five project is ten years old. It is only recently, from the official announcement of the RISC-V Foundation, that we know that the project was started in 2010.<\/p>\n\n\n\n

“After careful perusal of old email files, we\u2019ve decided that May 18th, 2010, was the day when we finally decided to develop our own clean-slate ISA, and so we\u2019re using this as the official birthday of RISC-V, even though the actual name came a bit later.” <\/p>\n\n\n\n

It is very exciting to see for only 10 years, RISC-V has achieved so many things and is still growing fast. RISC-V is bringing a revolution to the world, let’s evolve in the revolution, and looking forward to more things that RISC-V will bring to us.<\/p>\n\n\n\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

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