{"id":36502,"date":"2020-09-30T20:26:21","date_gmt":"2020-09-30T12:26:21","guid":{"rendered":"\/blog\/?p=36502"},"modified":"2020-09-30T20:26:24","modified_gmt":"2020-09-30T12:26:24","slug":"analog-to-digital-converter-ads1015","status":"publish","type":"post","link":"https:\/\/www.seeedstudio.com\/blog\/2020\/09\/30\/analog-to-digital-converter-ads1015\/","title":{"rendered":"Analog to digital converter\u2014\u2014ADS1015"},"content":{"rendered":"\n
\"\"
Ref: ADS1015<\/a> <\/figcaption><\/figure><\/div>\n\n\n\n

ADS1015 is an AD conversion chip produced\nby TI. It adopts IIC serial protocol communication, 4 conversion channels,\n12-bit conversion accuracy, maximum conversion speed of 3.3ksps, built-in gain\namplifier, users can set the gain according to their needs. The same series as\nADS1015 also has ADS1016, 16-bit conversion accuracy.<\/p>\n\n\n\n

In addition, AIN0 and AIN1 can be used for\ndifferential measurement with AIN3. Configure the multiplexer in MUX[2:0 of the\nconfiguration register. ]<\/p>\n\n\n\n

When measuring a single-ended signal, the\nnegative input of the ADC is internally connected to GND through a switch in\nthe multiplexer.<\/p>\n\n\n\n

ADS101x uses a switched capacitor to\ncontinuously charge and discharge the capacitor in the input stage to measure\nthe voltage between AINP and AINN. The ADS101x has a 1-MHz internal oscillator,\nwhich is divided by 4 to produce an fMOD of 250 kHz. The capacitance used in\nthis input stage is very small, and the average load is resistive to the\nexternal circuit. Figure 11 shows this structure. The capacitance value sets\nthe resistance and switching rate.<\/p>\n\n\n\n

During the sampling phase, switch S1 is closed. This allows CA1 to V(AINP), CA2 to V(AINN), CB to (V(AINP)-V(AINN)). In the discharge phase, S1 is first opened, and then S2 is closed. Then CA1 and CA2 are discharged to approximately 0.7 V, and CB is discharged to 0 V. This charging will draw a very small transient current from the power supply driving the analog input of the ADS101x. <\/p>\n\n\n\n

Pin introduction of ADS1015<\/h2>\n\n\n\n
\"\"
Ref: Pin of ADS1015 <\/a><\/figcaption><\/figure><\/div>\n\n\n\n

1. ADDR address pin (connect to different\npins to set different addresses, the address of the GND pin is 0x48)<\/p>\n\n\n\n

2. ALERT interrupt pin, voltage comparison\ncan be configured in the chip, which can be used as a numerical comparator output\nor conversion ready pin<\/p>\n\n\n\n

3.GND ground wire<\/p>\n\n\n\n

4.AIN0 AD conversion channel 0<\/p>\n\n\n\n

5.AIN1 AD conversion channel 1<\/p>\n\n\n\n

6.AIN2 AD conversion channel 2<\/p>\n\n\n\n

7.AIN3 AD conversion channel 3<\/p>\n\n\n\n

8. Connect VDD to 2.0-5.5V<\/p>\n\n\n\n

9. SDA IIC data cable<\/p>\n\n\n\n

10.SCL IIC clock line<\/p>\n\n\n\n

The pins can set different addresses according to the four pins connected to GND, VDD, SDA, SCL, as shown in the following table:<\/p>\n\n\n\n

\n ADDR PIN\n <\/td>\n SLAVE ADDRESS\n <\/td><\/tr>
\n Ground\n <\/td>\n 1001000\n <\/td><\/tr>
\n VDD\n <\/td>\n 1001001\n <\/td><\/tr>
\n SDA\n <\/td>\n 1001010\n <\/td><\/tr>
\n SCL\n <\/td>\n 1001011\n <\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Register of ADS1015<\/h2>\n\n\n\n

ADS1015 has four registers, as shown in the figure below, BIT1 and BIT0 represent the address of the register, corresponding to the conversion register, configuration register, low threshold register and high threshold register respectively. Among them, the conversion register stores the result of AD conversion. Since the conversion result is 12 bits, the data should be shifted to the left by 4 bits when reading, the register is configured to configure the chip parameters, and the high threshold and low threshold registers are used as voltage comparison functions.<\/p>\n\n\n\n

\n BIT1\n <\/td>\n BIT0\n <\/td>\n REGISTER\n <\/td><\/tr>
\n 0\n <\/td>\n 0\n <\/td>\n Conversion\n register\n <\/td><\/tr>
\n 0\n <\/td>\n 1\n <\/td>\n Config\n register\n <\/td><\/tr>
\n 1\n <\/td>\n 0\n <\/td>\n Lo_thresh\n register\n <\/td><\/tr>
\n 1\n <\/td>\n 1\n <\/td>\n Hi_thresh\n register\n <\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Register related configuration<\/h2>\n\n\n\n

The configuration register is needed to configure the ADS1015 chip, as shown in the following table:<\/p>\n\n\n\n

\n BIT\n <\/td>\n 15\n <\/td>\n 14\n <\/td>\n 13\n <\/td>\n 12\n <\/td>\n 11\n <\/td>\n 10\n <\/td>\n 9\n <\/td>\n 8\n <\/td><\/tr>
\n NAME\n <\/td>\n OS\n <\/td>\n MUX2\n <\/td>\n MUX1\n <\/td>\n MUX0\n <\/td>\n PGA2\n <\/td>\n PGA1\n <\/td>\n PGA0\n <\/td>\n MODE\n <\/td><\/tr>
\n  \n <\/td><\/tr>
\n BIT\n <\/td>\n 7\n <\/td>\n 6\n <\/td>\n 5\n <\/td>\n 4\n <\/td>\n 3\n <\/td>\n 2\n <\/td>\n 1\n <\/td>\n 0\n <\/td><\/tr>
\n NAME\n <\/td>\n DR2\n <\/td>\n DR1\n <\/td>\n DR0\n <\/td>\n COMP_MODE\n <\/td>\n COMP_POL\n <\/td>\n COMP_LAT\n <\/td>\n COMP_QUE1\n <\/td>\n COMP_QUE0\n <\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Several important register configurations:<\/p>\n\n\n\n

(1) BIT[15] OS bit: This is to set the mode\nof chip data reading, whether it is single reading or continuous reading.<\/p>\n\n\n\n

(2)BITS[10-11]: Configure voltage gain.<\/p>\n\n\n\n

(3)BITS[7-5]: Configure the conversion speed.<\/p>\n\n\n\n

I2C interface<\/h2>\n\n\n\n

ADS101x communicates via I2C interface. I2C\nis a two-wire open-drain communication interface that supports multiple devices\nand hosts on the same bus. Devices can drive the bus only by pulling the bus\nlow by themselves, and cannot drive the bus when the bus is high. Therefore,\nthe bus requires a pull-up resistor, so when there is no device driving the\nbus, the bus is always high. In this way, there is no conflict. If two devices\ndrive the bus at the same time, there is no drive contention. Communication on\nthe bus always takes place between two devices, one as the master and the other\nas the slave. Both the master and the slave can read and write, but the slave\ncan only read and write under the request of the master. So I2C devices can be\nused as master or slave, but ADS101x can only be used as slave.<\/p>\n\n\n\n

An I2C bus contains two lines: SDA and SCL.\nSDA transmits data; SCL provides clock. All data transmitted through I2C is a\ngroup of 8 bits. When SCL is low, drive the SDA line to send data to the I2C\nbus (low level means 0, high level means 1). After the SDA line data is\nprepared, the SCL line is pulled high and then pulled low. Through such pulses,\nSDA puts the data in the shift register. If the bus remains idle for more than\n25ms, the bus will time out.<\/p>\n\n\n\n

The I2C bus is bidirectional, that is, the\nSDA line both receives and sends data. When the host reads data from the slave,\nthe slave drives the data line, and when the host sends data to the slave, the\nhost drives the data line. The clock line is always driven by the host. ADS101x\ncannot be used as a host, so it cannot drive the SCL clock line. When\ncommunication occurs, the bus starts to change. Only the host can start a\ncommunication and establish a start condition. Under normal circumstances, the\ndata line changes state only when the clock line is low. If the data line\nchanges state when the clock line is high, it means another communication start\nor end condition. The establishment of the start condition requires that when\nthe clock line is high, the data line changes from high to low.<\/p>\n\n\n\n

The establishment of the end condition\nrequires that when the clock line is high, the data line changes from low to\nhigh.<\/p>\n\n\n\n

After establishing a start condition, the\nhost needs to send a byte to indicate which device to communicate with. This\nbyte is called the address byte. Each device on the I2C bus has a unique 7-bit\naddress to respond. The host sends a bit along with the address byte to\nindicate whether it needs to be read or written. Every byte (address or data)\nsent on the bus will be acknowledged by an acknowledge bit. After the master\nsends a byte (8 bits) to the slave, the master releases the data line and waits\nfor the response from the slave. The response of the slave is indicated by\npulling down the data line. The host then continues to send clock pulses to\nrecord this response. Similarly, when the host finishes reading a byte, the\nhost pulls down the data line to indicate a response to the slave. The host\ncontinues to send clock pulses to record this response. The clock line is\nalways driven by the host.<\/p>\n\n\n\n

If the host tries to communicate with a device\nthat is not on the bus, it will receive a non-response, because there is no\ndevice at that address to pull down the data line to answer the host. The\nnon-response performance is as long as the data line is kept high during the\nresponse period.<\/p>\n\n\n\n

When the master and slave end\ncommunication, an end condition needs to be established. When the end condition\nis established, the bus resumes the idle state. At this time, the host can\nestablish another start condition. Establishing a start condition when the bus\nis in use is called repeated start.<\/p>\n\n\n\n

The development of a product is inseparable from PCB assembly. In order to make the product performance more reliable. For more details about the product ADS1015, please click Seeed Fusion<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"

ADS1015 is an AD conversion chip produced by TI. It adopts IIC serial protocol communication,<\/p>\n","protected":false},"author":40,"featured_media":36503,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_lmt_disableupdate":"","_lmt_disable":"","_price":"","_stock":"","_tribe_ticket_header":"","_tribe_default_ticket_provider":"","_tribe_ticket_capacity":"0","_ticket_start_date":"","_ticket_end_date":"","_tribe_ticket_show_description":"","_tribe_ticket_show_not_going":false,"_tribe_ticket_use_global_stock":"","_tribe_ticket_global_stock_level":"","_global_stock_mode":"","_global_stock_cap":"","_tribe_rsvp_for_event":"","_tribe_ticket_going_count":"","_tribe_ticket_not_going_count":"","_tribe_tickets_list":"[]","_tribe_ticket_has_attendee_info_fields":false,"iawp_total_views":0,"footnotes":""},"categories":[1],"tags":[],"class_list":["post-36502","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"yoast_head":"\nAnalog to digital converter\u2014\u2014ADS1015 - Latest News from Seeed Studio<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.seeedstudio.com\/blog\/2020\/09\/30\/analog-to-digital-converter-ads1015\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Analog to digital converter\u2014\u2014ADS1015 - Latest News from Seeed Studio\" \/>\n<meta property=\"og:description\" content=\"ADS1015 is an AD conversion chip produced by TI. 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