What Is I2C<\/h3>\n\n\n\n
I\u00b2C (Inter-Integrated Circuit)<\/strong> is a serial communication bus<\/strong> that uses a multi-master-slave architecture. It was designed by Philips in the early 1980s (now NXP Semiconductors). I2C is convenient for motherboards, embedded systems, or Communication between cell phones and peripheral components. Due to its simplicity, I2C is widely used for communication between microcontrollers and sensor arrays, displays, IoT devices, EEPROMs, etc. I2C consists of two lines, SCL and SDA. These two data lines need to be connected to pull-up resistors. When the bus is idle, SCL and SDA are at a high level. The I2C bus works according to a certain protocol. Next, let’s take a look at the I2C protocol. I2C supports multiple slaves, that is, multiple I2C slave devices can be attached to one I2C controller. These different I2C slave devices have different device addresses so that the I2C master controller can access the specified device address through the device address of the I2C device. I2C device, one I2C bus connects multiple I2C devices as shown in the figure:<\/p>\n\n\n\n SDA and SCL links must be connected to a pull-up resistor, usually 4.7K. The rest of the I2C slaves are hooked up to the SDA and SCL lines so that multiple I2C devices can be accessed via the SDA and SCL lines.<\/p>\n\n\n\n Maybe you are still confused about I2C, here are some features of I2C<\/p>\n\n\n\n 1. Only one data line SDA and one clock line SCL are required, SDA<\/strong> (serial data line) and SCL<\/strong> (serial clock line) are both bidirectional I\/O lines<\/p>\n\n\n\n SCL (Serial Clock): <\/strong>Serial clock line, which transmits CLK signals, generally provided by the master device to the slave device<\/p>\n\n\n\n SDA (Serial Data): <\/strong>serial data line, transmit communication data<\/p>\n\n\n\n 2. Realize a real multi-master bus, any device can be used as both a master and a slave, but there can only be one master at the same time<\/p>\n\n\n\n 3. It can be detected by external connection, which is convenient for system fault diagnosis and debugging<\/p>\n\n\n\n 4. ICs connected to the same bus are only limited by the maximum capacitance of the bus. The serial 8-bit bidirectional data transfer bit rate can reach 100Kbit\/s<\/strong> in standard mode, 400Kbit\/s<\/strong> in fast mode, and up to 3.4Mbit\/s<\/strong> in high-speed mode.<\/p>\n\n\n\n 5. The current consumed on the bus is very small. Therefore, the number of devices expanded on the bus is mainly determined by the capacitive load, which is resistant to high noise interference<\/strong>. Adding a bus driver can expand the bus capacitance by 10<\/strong> times, and the transmission distance can reach 15m<\/strong>; compatible with different voltage levels devices with a wide operating temperature range<\/p>\n\n\n\n 6. The interface circuit is an open-drain output. It needs to be connected to the power supply VCC through a pull-up resistor. When the bus is idle, both lines are high. The external devices connected to the bus are CMOS devices. The output stage is also an open-drain circuit.<\/p>\n\n\n\n The master device and slave device follow the following protocol format for data transmission. Data transfer serial data of 0 and 1 between the master and slave devices over an SDA data line, The structure of a serial data sequence can be divided into:<\/p>\n\n\n\n When the master device decides to start communication, it needs to send a start signal, and the following actions need to be performed<\/p>\n\n\n\n After the master device has signaled and started condition, all slaves will become active even in sleep mode<\/strong> and wait to receive an address bit<\/strong>.<\/p>\n\n\n\n Address bits support 7bit and 10bit, If the master needs to send\/receive data to the slave, it must send the address first then the slave will correspond, and then match the address of the slave mounted on the bus.<\/p>\n\n\n\n Response Bit has 2 types:<\/p>\n\n\n\n Every time the master sends data and read and write bits, it will wait for the response signal ACK from the slave device.<\/p>\n\n\n\n Every time the data is transmitted has a total of 8 bits, which the sender sets and it needs to transmit the data bits to the receiver.<\/p>\n\n\n\n The transmission is followed by an ACK\/NACK bit, and if the receiver successfully receives the data, the slave sends an ACK. Otherwise, the slave sends a NACK.<\/p>\n\n\n\n Data can be sent multiple times until a stop bit is received.<\/p>\n\n\n\n When the master device decides to end the communication, it needs to send the end signal, and the following actions need to be performed.<\/p>\n\n\n\n Here\u2019s the figure showing the completed I2C timing diagram:<\/p>\n\n\n\n In a multi-main communication system. There are multiple nodes on the bus, they all have their own addressing addresses, they can be accessed by other nodes as slave nodes, and they can all be used as master nodes to send control bytes and transfer data to other nodes. But if two or more nodes both send start signals to the bus and start transmitting data, a conflict occurs. To resolve this conflict, an arbitration decision is required, which is arbitration on the I2C bus.<\/p>\n\n\n\n The arbitration on the I2C bus is divided into two parts: the synchronization of the SCL line<\/strong> and the arbitration of the SDA line<\/strong>.<\/p>\n\n\n\n SCL synchronization is due to the logic function of the bus line “AND” (open-drain output), that is, as long as one node sends a low level, the bus appears as a low level. The bus can only appear high when all nodes send high. It is precise because of the principle of the line “AND” logic function that when multiple nodes send clock signals at the same time, a unified clock signal is displayed on the bus. This is the synchronization principle of SCL<\/p>\n\n\n\n Arbitration of the SDA line is also based on the principle that the bus has a line “AND” logic function. After the node sends 1-bit data, it compares whether the data presented on the bus is consistent with what it sent (similar to the readback mechanism of the CAN bus). Yes, continue sending; otherwise, exit the competition. Arbitration of the SDA line can ensure that the I2C bus system communicates normally and data is not lost when multiple master nodes attempt to control the bus at the same time. The bus system allows only one master node to continue to occupy the bus through arbitration.<\/p>\n\n\n\n DATA1 and DATA2 are respectively the data signals sent by the master node to the bus, SDA is the data signal presented on the bus, and SCL is the clock signal presented on the bus. When master nodes 1 and 2 send start signals at the same time, both master nodes send high-level signals. At this time, the signal on the bus is high, and both master nodes detect that the signal on the bus is the same as the signal sent by themselves, and continue to send data. In the second clock cycle, both master nodes send low-level signals, and the signals presented on the bus are low-level and continue to send data. In the 3rd clock cycle, master node 1 sends a high-level signal, while master node 2 sends a low-level signal. According to the logic function of the line “AND” of the bus, the signal on the bus is low level. At this time, master node 1 detects that the data on the bus is different from the data sent by itself, and disconnects the output stage of the data, and turns to The slave to receive the status. In this way, master node 2 wins the bus, and the data is not lost, that is, the data on the bus is the same as the data sent by master node 2, and master node 1 continues to receive data after turning into a slave node, and also does not lose the SDA line. data. Therefore data is not lost during the arbitration process.<\/p>\n\n\n\n Summary<\/strong>: SDA arbitration and SCL clock synchronization processing are not sequential, but are carried out at the same time.<\/p>\n\n\n\n In actual use, I2C is prone to deadlock. There are two common situations in which deadlocks occur:<\/p>\n\n\n\n The same point in both cases is that SDA is in a state of being pulled low by the slave device when the master device is reset abnormally, while SCL is in a VOH (idle state) after the master device is reset. At this point, the slave device will wait for the master device to pull SCL low to take the ACK or data bit, and the master device will wait for the slave device to release the SDA line. The master device and the slave device wait for each other, look at each other in the air, and enter a deadlock state.<\/p>\n\n\n\n Here are some common methods to solve deadlock problem\uff1a<\/p>\n\n\n\n The I2C deadlock problem cannot be fundamentally avoided. In addition to the I2C deadlock caused by the abnormal reset of the MCU, the slave device may also pull down the SDA abnormally to cause the deadlock during the normal communication process. Therefore, the software should be designed to be able to recover from the deadlock when the deadlock occurs, so that the I2C communication can continue.<\/p>\n\n\n\n What is I2C Clock Stretching? In the master-Slave communication process of I2C, the SCL clock on the bus is always generated and controlled by the master, but if the slave cannot keep up with the speed of the master, the I2C protocol stipulates that the slave can pull down the SCL clock line. A transfer is suspended until the slave releases the SCL line, and the transfer continues.<\/p>\n\n\n\n Clock Stretching is an optional configuration for the slave. If it is not enabled, the slave cannot control SCL; if it is enabled, the slave can reduce the transmission speed by forcibly pulling SCL low. During the period when SCL is VOL, the host can only wait for the Slave releases SCL.<\/p>\n\n\n\n Sometimes the master needs to perform multiple message exchanges in one communication such as transferring messages with different slaves, or switching read and write operations, and does not want to be interfered with by other master during this period, then you can use the \u2018repeat start condition\u2019 —In a communication, the master can generate multiple start conditions to complete multiple message exchanges, and finally generate a stop condition to end the entire communication process. Since there is no stop condition during the period, the master keeps occupying the bug, and the other mains cannot switch in.<\/p>\n\n\n\n Here’s the difference between UART, I2c, and SPI <\/p>\n\n\n\n![\"\"](\"https:\/\/www.seeedstudio.com\/blog\/wp-content\/uploads\/2022\/09\/I2C1.png\")
Features of I2C:<\/h3>\n\n\n\n
Data Transmission\uff1a<\/h3>\n\n\n\n
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Start Bit<\/h3>\n\n\n\n
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Address Bit<\/h3>\n\n\n\n
Response Bit <\/h3>\n\n\n\n
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Data Bit<\/h3>\n\n\n\n
Stop Bit<\/h3>\n\n\n\n
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Multi-Main Arbitration<\/h2>\n\n\n\n
Synchronization of The SCL Line (Clock Synchronization)<\/h3>\n\n\n\n
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SDA Arbitration<\/h3>\n\n\n\n
Arbitration Process<\/h3>\n\n\n\n
I2C Deadlock<\/h3>\n\n\n\n
Clock Stretching<\/h2>\n\n\n\n
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Repeat Start<\/h2>\n\n\n\n
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