Bus Blaster v4

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An experimental, high-speed JTAG debugger Compatible with many different JTAG debugger types ships with JTAGkey compatible buffer image pre-programmed Support Serial Wire Debug when available Open Source
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Bus Blaster v4 is an experimental, high-speed JTAG debugger from Dangerous Prototypes.

Thanks to a reprogrammable buffer, a simple update over USB makes Bus Blaster compatible with many different JTAG debugger types in the most popular open source software.

  • Based on FT2232H with high-speed USB 2.0

  • Buffered interface works with 3.3volt to 1.8volt targets

  • Reprogrammable buffer is compatible with multiple debugger types

  • Compatible with 'jtagkey', 'KT-link' programmer settings in OpenOCD, urJTAG, and more

  • ships with JTAGkey compatible buffer image pre-programmed

  • Should support Serial Wire Debug when available

  • Mini-CPLD development board: self programmable, extra CPLD pins to header

  • Open source (CC-BY-SA)

    • Bus Blaster Manual

    • Bus Blaster design overview

    • Bus Blaster forum

    • CPLD buffer logic overview

    • V4 uses a larger CPLD than previous versions. It can now support the SWV feature of Cortex microcontroller for advance debugging when software support is available

    • ŸSWV is little used and not currently supported in software, most users will be better off with Bus Blaster v3 available here

    • Fitted in a DP9056 (90x56 mm) standard PCB

    • Added series resistors to input and output pins to protect against damage and noise

Updates in v4:

Each unit is tested before it ships.

This open source hardware and software is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.


This product is designed by Dangerous, If you encounter any problems when using this product, please request technical support in the forum.

Technical details

Dimensions 0mm x0mm x0mm
Weight G.W 26g
Battery Exclude


HSCODE 8538900000
USHSCODE 8471500150
UPC 841454111238
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Customer Reviews
    Which buffer logic was loaded into the CPLD by the factory? It didn't work with OpenOCD in any mode, JTAGKey or KT-Link. I had to find a matching bitstream on the Internet and luckily found a project on github from some guy who had ported the v3 buffer logic to the bigger CPLD of the v4. It works now, but the documentation was really lacking.

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    JTAG Programming Xilinx XC2C256 Works fine with urjtag command line tool. Programming without errors and without great issues. Excellent low cost tool.

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