Sipeed Tang Nano FPGA Board Powered by GW1N-1 FPGA

Main Features

• GW1N-1-LV:1152 LUT4, 864 FF(Flip-Flop)
• 72K B-SRAM(bits); 96K user flash(bits); 1 PLL
• Support a 5 inches 800*480 screen
• Onboard JTAG Downloader
• Not support for DSP
• Small size, low cost

Description

You may not believe in your eyes when you see such a low price FPGA development board, but it is true! This Sipeed Tang Nano FPGA board powered by GW1N-1 FPGA  board will be a nice choice for you to accomplish some subentries. Don’t worry about its small size; it is well equipped with many elements for an FPGA development board.

Sipeed Tang Nano FPGA board powered by GW1N-1 FPGA board carries a low power core chip GW1N-1-LV, this chip has 1152 LUT4 which contains 4 address for RAM and 864 FF(Flip-Flop). The block SRAM in this tiny FPGA board is 72K, so you have 72kbits to save data. Unfortunately, due to the size limitation, this board doesn’t include a DSP module, as a matter of fact, you can’t do the complex calculation like accumulation or multipliers cascading based on this board.

Besides those main features for an FPGA board above, this board contains rich I/O PINs with the number of 34 and a USB Type-C interface for the power supply and downloading code. There is a  JTAG downloader on the FPGA board, so you can simply use a USB cable connecting to the board to download the code without an extra downloader outside the board. The most important feather is that this board has a 40 Pin FPC LCD carrier which means a 40 PIN RGB LCD Screen can be equipped on the board! The 5 inches 800*480 screen is especially compatible with this FPGA board, for your better experience with the board, we suggest you purchase them in a bundle.

Tang nano framework

Specification

• FPGA chip GWIN-1-LV: LUT4 1152, Flip-Flop 864, BSRAM(bits) 72K, USER Flash(bits)  96K, PLLs+DLLs 1+0, Core voltage 1.2V
• Download method: Simply plug in the USB cable and download it via the onboard downloader.
• Power circuit: Each Bank occupies a separate LDO power chip (except BANK0/3). Adjust the I/O level of BANK1 and BANK2 by replacing the LDO chip by yourself.
• 40P FPC LCD carrier: Standard 40 RGB LCD interface. On-board screen backlight driver circuit(default normally open, EN pin can be connected to FPGA)
• I/O: 34 I/O ports and multiple power pins on both sides. Both sides of the pins can be directly inserted into the breadboard.
• Onboard PSRAM chip: Capacity: 64Mbits Voltage: 3.3V
• Power supply and download interface: USB-Type-C interface
• RGB LED: Onboard small size RGB LED
• Button: 2 3X4mm buttons onboard
• Crystal oscillator: Onboard 24Mhz crystal oscillator(started by CH552)
• External supply voltage demand: 5.0V±0.2V
• External supply current demand: >400mA@5V
• Temperature rise: <30K
• Range of working temperature: −30°C~50°C

Dimensions

If you would like to use more FPGA boards for further study or work, we recommend the following board.

• Spartan Edge Accelerator Board - Arduino FPGA Shield with ESP32
• Perf-V Based on Xilinx Artix-7 FPGA RISC-V opensource
• Perf-V Based on Xilinx Artix-7 FPGA RISC-V opensource - XC7A100T-1FTG256C
• Papilio Pro
• Papilio One 250K
• Papilio DUO-512KB
• Papilio DUO-2MB