What is RISC-V？10 Things You Should Know in 2026
Updated May 2026 — Originally published June 2020 by Pham Nuwen
1. What is RISC-V
RISC-V (“risk-five”) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open-source operating systems are available and the instruction set is supported in several popular software toolchains.
An Instruction Set Architecture (ISA) is essentially the language a processor speaks — it defines what commands the chip understands and how software talks to hardware. x86 is the language your laptop’s Intel or AMD processor speaks. Arm is what powers most smartphones. RISC-V is the open-source alternative.
2. It Started at UC Berkeley in 2010
RISC-V was born in 2010 as a research project at the University of California, Berkeley, led by professors Krste Asanović and David Patterson. The “V” in RISC-V stands for the fifth generation of RISC research coming out of Berkeley — a lineage going back to the 1980s.
The original goal was modest: create a clean, simple ISA for research and teaching without the baggage of decades of legacy decisions baked into x86 or Arm. What no one quite predicted was that “clean and simple” would turn out to be exactly what the industry had been waiting for.
3. The Design Is Modular — Base ISA Plus Extensions
The RISC-V instruction set has modular characteristics. The instruction set is organized in a modular manner. Each module is represented by an English letter. The instruction set includes the standard part and the extension part. The standard part must be implemented.
For example: If you want to implement a 32-bit architecture RISC-V processor, the RV32I instruction set must be implemented on the hardware. The basic integer ISA and the machine privilege ISA provide the functions required by the basic general-purpose CPU. Developers can also enhance the processor’s functionality by adding extensions to ISA.
4. Why RISC-V? The Case Beyond "It's Free"
- Free: RISC-V is open-source, there is no need to pay for the IP.
- Simple: RISC-V is far smaller than other commercial ISAs.
- Modular: RISC-V has a small standard base ISA, with multiple standard extensions.
- Stable: Base and first standard extensions are already frozen.
- Extensibility: Specific functions can be added based on extensions.
Customizability is arguably more valuable for many use cases. With Arm, you can configure what’s offered; with RISC-V, you can add entirely new instructions tailored to your workload. Google, for instance, has deployed custom RISC-V cores inside its Tensor chips for specific ML tasks (source: Tom’s Hardware).
Academic transparency still matters too. RISC-V’s clean design makes it genuinely easier to teach, research, and verify — which feeds a virtuous cycle of talent entering the ecosystem.
5. Where Is RISC-V Being Used Today?
This is where the 2020 version of this article aged the most. Back then, RISC-V was exciting but peripheral. Today, it’s in production at scale across multiple segments.
IoT and Embedded
- Sophgo’s SG200X series, which powers Seeed Studio reCamera for edge vision AI applications;
- Microchip’ s PolarFire® MPFS025T, a 5-core RISC-V SoC used in the BeagleV platforms;
- and Bouffalo Lab’ s BL808, a heterogeneous RISC-V processor featured in products such as the Sipeed M1s module.
AI and Data Center
Qualcomm‘s acquisition of Ventana Micro Systems and Meta’s acquisition of Rivos marked the point where RISC-V stopped being a startup story and became a strategic asset for the biggest names in tech. ESWIN‘s EIC7702X delivered competitive performance in 2025, and second-generation RISC-V laptops are expected to reach consumers soon.
Industrial and Automotive
ISO 26262 functional safety certification processes now support RISC-V, opening the door to automotive applications. Industrial automation, where the ability to customize the ISA for real-time control tasks is genuinely valuable, is another area of growing adoption.
6. Who Is Behind RISC-V?
RISC-V International has over 4,000 members across 70+ countries, ranging from research universities to the largest semiconductor companies in the world. (https://riscv.org/members/)
Chip and IP companies made up the largest block, followed by software (dev tools, firmware, OS), research institutions, and industry verticals (automotive, cloud, HPC). By 2025, the balance has shifted noticeably toward software and vertical industry members
7. The Software Ecosystem
The biggest knock on RISC-V in 2020 was software. That critique aged fast.
The foundation is now solid. GCC and LLVM treat RISC-V as a first-class target alongside x86 and Arm — no special flags, no workarounds. The Zephyr RTOS fully supports RISC-V including Nordic’s nRF54L Series. FreeRTOS and NuttX both have mature RISC-V ports. For embedded developers, the toolchain question is largely settled.
The bigger 2025 story is what happened at the application layer. The RISE project (RISC-V Software Ecosystem) — backed by Google, Intel, Qualcomm, Red Hat, Samsung, and others — funded and coordinated critical work across Go, Java, PyTorch, llama.cpp, and IREE on RISC-V.
8. RISC-V vs Arm
Media coverage tends to frame RISC-V and Arm as locked in existential combat. The reality in 2026 is more interesting.
Yes, RISC-V has captured real market share, and yes, there are segments where it’s actively displacing Arm. But many of the most sophisticated chips being designed right now use both architectures. Why? The answer gets into architecture philosophy, workload partitioning, and why “which is better” is often the wrong question entirely. We will cover it in depth in our dedicated piece soon. Stay tuned!
9. How to Get Started with RISC-V
The easiest way to start is with hardware you can buy today.
If you’re new to embedded, Espressif‘s ESP32-C series are the most accessible entry points — cheap, well-documented, supported by Arduino and the ESP-IDF framework, and already shipping in millions of products. The C6 adds Wi-Fi 6 and Zigbee support.
If you’re building low-power wireless devices: The Seeed XIAO nRF54LM20A (coming soon) brings the Nordic nRF54LM20A into the XIAO form factor — Arm Cortex-M33 + RISC-V coprocessor, BLE 6.0, Matter/Thread support, up to 66 GPIOs, 2MB NVM, 512KB RAM, all in a board the size of your thumb. It’s a practical way to work with both architectures in a production-ready package.
If you’re coming from the software side: The RISC-V toolchain is well-integrated into standard development environments. GCC and LLVM support is solid; Zephyr, FreeRTOS, and NuttX all have RISC-V targets. The RISC-V Getting Started Guide is a reasonable starting point.
10. What's Coming Next
Several trends are already becoming clear:
- AI acceleration and custom silicon. Companies building AI hardware increasingly want specialized instructions optimized for machine learning workloads. RISC-V’s extensibility makes it well-suited for this trend.
- Higher-performance processors. Early RISC-V success came from microcontrollers and embedded systems. Today, companies such as ESWIN, Ventana, and Alibaba’s T-Head are pushing into application processors capable of running desktop Linux and more demanding workloads.
- Automotive and industrial adoption. As functional safety certifications mature, RISC-V is becoming a viable option for automotive electronics, industrial automation, and other long-lifecycle systems.
- A stronger software ecosystem. Efforts such as RISE are accelerating support across operating systems, compilers, AI frameworks, and developer tools, making it easier than ever to build software for RISC-V platforms.
End Note
RISC-V’s journey from a Berkeley classroom project to a quarter of the global processor market in 15 years is genuinely one of the more remarkable stories in semiconductor history. The more interesting question is what gets built with it next.
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