Xilinx SEA-7 FPGA Projects Collections – from Xilinx Summer School

01 – 2020 New Engineering Alliance-Xilinx Summer School Introduction

The summer school sponsored by the Information Technology New Engineering Alliance and jointly sponsored by Xilinx, Southeast University and Southwest Jiaotong University will end on August 3rd. During the fifteen days from July 20th to August 3rd, more than 1,200 students participated in this summer school through the Internet all over the world.

After 100 hours of practice

  • What did you learn during the first week of courses and experiments?
  • What was the result of the project practice in the second week?
  • What can the zero-based students of Class A accomplish?
  • How advanced is the HLS design of Class B? We invite you to review!

02 – Introduction to Excellent Works of Class A

A1.The gesture of Rock-Paper-Scissors game recognition based on OV5647

Introduction:

The project is based on the SEA-S7 platform to realize gesture recognition, which can recognize scissors, rock, and paper gestures and compete with FPGA to get the result of the Rock-Paper-Scissors game. Players can interact with FPGA through the host computer to get the results and process data, which is convenient for players to expand their applications.

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A2.FPGA-based number recognition

Introduction:

This project is modified based on the Camera_Demo official routine, adding the functions of image processing and number recognition, that is, grayscale processing and binarization processing of the collected images, and then classification according to (0-9) digital features, and can display the measured number through the external LCD1602 or serial monitor. The processed image can be observed through the HDMI external screen. Results display:

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A3.Arbitrary Waveform Generator

Introduction:

This arbitrary waveform generator can remotely configure the relevant parameters of the waveform through WIFI, so that the DAC902 can output the analog signal that meets the requirements, and can also receive the relevant parameter information of the arbitrary waveform generator remotely in real time.

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A4.Arbitrary waveform generator + low pass filter (IP core implementation)

Introduction

The arbitrary waveform generator is realized, which can generate sine waves, square waves, triangle waves and sawtooth waves with frequencies of 1Hz, 10Hz, 100Hz…1MHz. Since there is no oscilloscope, the waveform generator board-level debugging only verifies the UART serial port transmission. The algorithm function of designing low-pass filter is not realized, and finally the low-pass filter simulation is realized with IP core.

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A5.Multi-channel UART/SPI expansion

Introduction:

Realize according to the button switch communication mode, choose between UART and SPI, and can realize the communication between the SPI master (or UART sending end) and multiple SPI slaves (or UART receiving end), and the slave can be realized in the communication process (Or receiving end) address selection.

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A6.Classic Game Reappearance: Dodge the Car

Introduction:

Mini-game ‘dodge the car’. The player controls the car with two buttons on the control panel, and chooses the avoidance direction according to the obstacle.

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A7.SEA-Catmario

Introduction:

Compared with the existing game examples, it realizes the functions of the game character jumping and displaying the map in blocks, which increases the complexity of the game.

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A8.Number recognition

Introduction:

This project can accurately identify a number with a pure background color, and select the number in the digital meter at the upper left corner of the display to keep it stable.

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A9.Snake game based on SEA

Introduction:

Realize the game function, use character modulo to reduce memory, increase boot animation, texture design to increase game experience, and can choose Bluetooth/handle control.

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A10.Multifunctional Maker Lantern

Introduction:

Realize color recognition and display the image captured by the camera in real-time. It also adds a user interface, brightness adjustment, and manual color output.

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A11.Application of AES encryption algorithm based on SEA Board in AWS IoT

Introduction:

We designed an AES encryption and decryption device that can change the secret key at any time. The FPGA is used to implement the AES algorithm, the input data is encrypted to obtain the ciphertext, and the ciphertext is exchanged with the QSPI data of the ESP32 through the FPGA, and the ciphertext is transmitted to the AWS cloud through the ESP32 network.

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A12.Classic game reproduction: flappy bird

Introduction:

The Flappy bird classic game reproduction based on ESP32. The source code is written on the vivado platform and is visualized through HDMI, reproduces the basic functions of the game, and builds an algorithm that dynamically adjusts the difficulty based on the game score.

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A13.MD5 encryption and QSPI serial communication

Introduction:

Realize to send the encrypted data directly from the serial port, and directly read the obtained MD5 encrypted hash value from the FPGA and return it to the computer serial monitor.

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A14.Instrumentation:Virtual Oscilloscope

Introduction:

It can collect external analog signals or discrete signals, and transmit the data to the MCU. The MCU draws waveforms on the display according to the received data.

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03 – Introduction to Excellent Works of Class B

B1.Flower5: flower recognition device

Introduction:

This design uses the Ultra96 development board, the InceptionV3 network, and the Vitis-AI quantitative compilation toolchain to make a five-flower classification device. Use Xilinx’s DPU (Deep learning Processing Unit) IP and Vitis-AI toolchain to quickly deploy deep learning networks on FPGAs.

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B2.Design of Acceleration Circuit of Target Detection Network Based on FPGA

Introduction:

Based on the principles of SkyNet and iSmart2, this project builds a lightweight neural network mainly composed of 3×3 channel-by-channel convolution and 1×1 point-by-point convolution to complete target detection tasks. And designed the FPGA acceleration circuit module for these two types of convolution to increase the convolution operation speed. The total on-chip power consumption of the hardware circuit is only 2.322W, and the IoU reaches 0.573, which meets the design goal.

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B3.Deblurring system for out-of-focus image based on PYNQ-Z2

Introduction:

This work can read local pictures or camera input pictures on the PS side and then write them into the shared memory, and then the AXI bus controls the PL side to perform high-speed two-dimensional Fourier transform, matrix operation, inverse transformation, and other processing to achieve Wiener filter operation, the new picture obtained by the PS terminal is finally read to realize the deblurring of the image. But at present, only certain designated images can be deblurred, and it has no adaptive ability.

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B4.Design of SSD (Single Shot Multi-Box Detector) target detection system based on PYNQ

Introduction:

The project realized the transplantation of the SSD target detection network on the PYNQ platform. The design of convolution, pooling, and L2 norm unit is completed through HLS tools, and a network framework is built on the PYNQ platform to realize the extraction of the target in the input image and the location of the target in the image.

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B5.Traffic sign recognition

Introduction:

This design is a neural network structure formed by fine-tuning the parameters based on the network architecture of the neural network LeNet-5. After training with TensorFlow2, the weight parameters and bias parameters of each layer are obtained, and then the HLS is used to form the accelerator of the neural network on the PL end, and the weight and bias parameters are imported into the PL end to achieve the purpose of neural network acceleration. The purpose of this design is to accelerate the neural network to finally be able to recognize traffic signs. Among them, we used tensorflow2.x to build a neural network and train it, use HLS to quickly build a known network structure, and allocate space reasonably.

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B6.Handwriting recognition

Introduction:

Handwriting recognition is a common image recognition task. Different people have different handwriting styles and different sizes, which causes some difficulties for computers in handwriting recognition tasks. In this work, handwriting recognition network lenet-5 is deployed on FPGA to realize automatic handwriting recognition with higher efficiency and lower power consumption.

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B7. AI mask detection system

Introduction:

In response to the need for mask-wearing recognition in epidemic prevention and control, this article is based on Xilinx’s latest Vitis-AI tool, combined with a self-designed image recognition network, to quickly develop an AI mask-wearing recognition system. The final recognition rate can reach more than 88%, and it can distinguish the situation of wearing a mask correctly, covering the mouth, wearing a scarf, etc.

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B8.The HLS implementation of MD5 algorithm

Introduction:

This project uses the HLS development method to implement the MD5 algorithm on FPGA. The project realized two sets of data sharing schemes using DMA and BRAM respectively for PS/PL. After the final test on the PYNQ-Z2 platform, both sets of schemes have reached the expected low power consumption and high-performance goals.

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B9.LMS-based adaptive filter

Introduction:

The adaptive filter is a variable coefficient digital filter. Because it can dynamically adjust the filter coefficients according to the algorithm, it can always maintain good filter performance. First, perform simulation on MATLAB to verify the adaptability of adaptive filtering; then implement parallelization on HLS, and finally achieve LSM parallel computing power, automatic parameter adjustment, and other functions; finally download the IP to the board for testing, after repeated testing and optimization, finally realized the adaptive filtering based on HLS.

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B10.Accelerated implementation of compression algorithm based on pynq

Introduction:

In this design, it is planned to realize the compression and decompression of files, and at the same time optimize the signal processing and calculation-intensive functions involved in the compression to realize the accelerated processing. The ultimate goal of this design is to prove that when the algorithm is implemented on a fully parallelized hardware architecture (such as FPGA), the speed of the algorithm can be greatly improved. We will first use the C language to implement the code, then comprehensively implement it in Vivado HLS, and finally implement the hardware implementation on the FPGA board (pynq-z2), and use python in the jupyter notebook for functional verification.

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B11.Smart door lock based on ultra96

Introduction:

Our project is a smart door lock system based on MQTT, Flutter, Dlib and Ultra 96 boards. The APP side has the functions of adding devices, remote control, and video streaming. The device-side can recognize strangers and take pictures and send back and support multi-user operations. The server side is responsible for operations such as communication between devices.

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B12.Face emotion recognition system based on Ultra96 platform

Introduction:

This design is a facial emotion recognition system designed based on the Ultra96-V2 platform. It uses a convolutional neural network algorithm to build a model, recognizes seven facial expressions, and deploys the model on the Ultra96 platform based on the Vitis AI framework to speed up the model Inference speed, the final detection speed reaches about 250FPS.

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B13.Handwritten mathematical formula calculator

Introduction:

This project uses HLS to implement a handwritten mathematical formula recognition and calculation function calculator based on a convolutional neural network on the PYNQ-Z2 development board. It can recognize the handwritten mathematical formula input from the USB camera or the local picture and calculate the result of the formula.

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B14.Design of binocular vision reconstruction system

Introduction:

This project designed a binocular vision ranging system on PYNQ-Z2, through the incoming left and right eye pictures, correct and eliminate distortion on PYNQ-Z2, and use a stereo matching algorithm to calculate the parallax between the two cameras. Finally, the three-dimensional reconstruction is performed through the obtained disparity map and the corresponding mapping matrix to obtain the corresponding depth image.

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